Most microprocessors contain registers that are used in executing instructions. When the microprocessors execute instructions, data values are read from the registers and results of operations are written into the registers. For example, the instruction “ADD R1, R2, and R3” adds the values held in resisters R1 and R2 and puts the resulting sum into register R3. R1, R2, and R3 are identifiers associated with respective registers.
Traditional microprocessors sequentially execute instructions in a computer program (i.e., in the order that the instructions appear in the computer program). In the simplest case, an instruction is executed per a clock cycle. Many instructions, however, may take more than one clock cycle to execute.
Superscalar processors, in contrast to traditional microprocessors, may issue and receive multiple instructions per clock cycle. With such processors, an instruction can be executed in a single clock cycle if there are no data dependencies, procedural dependencies, or resource conflicts that prevent execution of the instruction.
High performance processors use out-of-order processing, that is the processors process the instructions non-sequentially. Such high performance processors typically do not have a fixed relationship between a register identified and the physical register referenced by the identifier. Thus, the identifier R1 may refer to a first physical register in one instruction and refer to a second physical register in another instruction. The identifiers reference logical resisters that are mapped to corresponding physical registers.
One challenge with such processors is to manage and track the usage of register values. One conventional approach is to define an in-order state for each register. For example, if an instruction has been executed and all other previous instructions have also been executed, the values generated by the instructions are stored as the register's in-order state. The instruction is then considered “retired”.
Another conventional approach to tracking and recycling physical register mappings is to create a single large structure to do all the work associated with tracking physical registers mappings. Such a structure would have to have one entry for each physical register. Each entry would have to contain information about that register's current status, i.e., whether it's free or in use. Maintaining the data in such a structure would be very complex because simultaneous reading and updating would have to be supported. Considering the size, it would be very prohibitive to make such a technique work effectively. Such a technique would require to much area, too much power, and would add too much complexity. This technique was conceivable in the past because the number of physical registers that were supported was much lower. With the advent of out of order processors, the number of supported physical registers has sky-rocketed.
There are a variety of different solutions that utilize separate register files for holding register values. The transient values of the registers can be stored in the reader buffer or an instruction window, or a temporary register array. The major problem is that register values are transferred from transient register storage to a register array or a register file holding the in-order register values.
The other aforementioned concepts are not efficient in handling the monitoring and tracking of physical registers. Therefore, there is a need to find a way to reduce the size of the memory structures needed for tracking and regulating the physical register assignments.